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Espressif Systems /ESP32-S2-ULP /SENS /SAR_COCPU_INT_ENA

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Interpret as SAR_COCPU_INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (COCPU_TOUCH_DONE_INT_ENA)COCPU_TOUCH_DONE_INT_ENA 0 (COCPU_TOUCH_INACTIVE_INT_ENA)COCPU_TOUCH_INACTIVE_INT_ENA 0 (COCPU_TOUCH_ACTIVE_INT_ENA)COCPU_TOUCH_ACTIVE_INT_ENA 0 (COCPU_SARADC1_INT_ENA)COCPU_SARADC1_INT_ENA 0 (COCPU_SARADC2_INT_ENA)COCPU_SARADC2_INT_ENA 0 (COCPU_TSENS_INT_ENA)COCPU_TSENS_INT_ENA 0 (COCPU_START_INT_ENA)COCPU_START_INT_ENA 0 (COCPU_SW_INT_ENA)COCPU_SW_INT_ENA 0 (COCPU_SWD_INT_ENA)COCPU_SWD_INT_ENA

Description

Interrupt enable bit of ULP-RISCV

Fields

COCPU_TOUCH_DONE_INT_ENA

TOUCH_DONE_INT interrupt enable bit
COCPU_TOUCH_INACTIVE_INT_ENA

TOUCH_INACTIVE_INT interrupt enable bit
COCPU_TOUCH_ACTIVE_INT_ENA

TOUCH_ACTIVE_INT interrupt enable bit
COCPU_SARADC1_INT_ENA

SARADC1_DONE_INT interrupt enable bit
COCPU_SARADC2_INT_ENA

SARADC2_DONE_INT interrupt enable bit
COCPU_TSENS_INT_ENA

TSENS_DONE_INT interrupt enable bit
COCPU_START_INT_ENA

RISCV_START_INT interrupt enable bit
COCPU_SW_INT_ENA

SW_INT interrupt enable bit
COCPU_SWD_INT_ENA

SWD_INT interrupt enable bit

Links

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Register License

Copyright 2023 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data